1. Field of the Invention
The present invention generally relates a dynamic random access memory, DRAM refresh method and apparatus. More particularly, this invention relates to a DRAM refresh scheme with different frequencies of refresh for active and standby mode.
2. Description of the Prior Art
FIG. 1a shows the prior art memory cell and its reading and writing sub-systems. The bit line, BL 110 is shown attached to the sense amplifier, SA 120. The BL 110 is also attached to the n-channel metal oxide semiconductor field effect transistor NMOS FET 130. The BL 110 is attached to the drain of the FET 130. The gate of the FET is attached to the WL, word line 140. The source of the FET 130 is labeled signal 150. The signal voltage 150 is maintained by charging a capacitor or memory cell 160. The memory cell logic value of ‘I’ or ‘0’ is dynamically stored in the capacitor 160. The other mode of the capacitor cell 160 is attached to ground 170.
FIG. 1b shows a prior art view of two adjacent word lines, WLn and WLn+1. The example of FIG. 1b shows WLn 115 being selected and WL n+1 125 not selected or not accessed. FIG. 1b illustrates the case of the charge stored on memory cell capacitor 155 is affected, disturbed, or even changed by the WL line switching at WLn 115.
The unselected memory cell 155 is attached to the source of NMOS FET 135. The gate of NMOS FET 135 is attached to word line WL n+1 125. This WL n+1 125 is not switched or accessed in this example of FIG. 1b. The idle memory cell voltage is 145. The other node of the idle memory cell capacitor 155 is attached to ground, 165. The bit line is 136.
In FIG. 1b, the memory cell 185 being accessed by WLn 115 is shown. The WLn 115 is attached to the gate of NMOS FET 175. The bit line is attached to drain node 176 of the FET 175. The source of FET 175 is attached to the memory cell capacitor 185.
When the active word line WLn 115 is switched high to a logical ‘1’. There is positive capacitive coupling between the 2 word lines WLn and WLn+1. As a result if WLn+1 goes high, there is positive coupling via the Cgs, gate-to-source capacitance of FET 135. This could result in a voltage increase 145 at the memory cell capacitor 155. If there was previously a logical ‘0’ stored in memory cell capacitor 155, the above word line coupling could cause a logical ‘0’ at memory cell 155 to falsely change to a logical ‘1’.
When the active word line WLn is switched low to a logical ‘0’. There is negative capacitive coupling between the 2 word lines WLn and WLn+1. As a result if WLn+1 goes low, there is negative coupling via the Cgs, gate-to-source capacitance of FET 135. This could result in a voltage decrease 145 at the memory cell capacitor 155. If there was previously a logical ‘1’ stored in memory cell capacitor 155, the above word line coupling could cause a logical ‘1’ at memory cell 155 to falsely change to a logical ‘0’.
U.S. Pat. No. 6,363,024 (Fibranz) “Method for Carrying Out Auto Refresh Sequences on a DRAM” describes a method of refresh sequences automatically. The auto refresh sequence on a DRAM that is divided into memory banks is synchronized with the clock signal acting on the DRAM.
U.S. Pat. No. 6,310,814 (Hampel, et al.) “Rambus DRAM (RDRAM) Apparatus and Method for Performing Refresh Operations” describes an apparatus and method for simultaneously refreshing first and second rows of memory cells in a dynamic random access memory (DRAM) includes a plurality of banks of memory cells organized in rows.
U.S. Pat. No. 6,212,599 (Baweja, et al.) “Method and Apparatus for a Memory Control System Including a Secondary Controller for DRAM Refresh During Sleep Mode” describes a memory control system which includes a first memory controller designed to access and refresh a DRAM, using a clock, during a first operation mode.
U.S. Pat. No. 6,094,705 (Sony) “Method and System for Selective DRAM Refresh to Reduce Power Consumption” describes a method and system for selective refresh for a memory array is disclosed. The method and system comprises providing a plurality of valid bits, each of the valid bits is associated with a row of the memory device.